////////////////////////////////////////////////////////////////////////////// 
//
//  dwc_e12mp_phy_x4_ns_lane_if_assertions.v
//
//  Description: This is the PHY lane interface assertions file.
//
//  Author: Singer Wang,  Danny David
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////

`timescale 1ns/10fs

module dwc_e12mp_phy_x4_ns_lane_if_assertions (
  input vph,
`ifdef DWC_C10_PMA
	input [`DWC_E12MP_X4NS_TX_CLK_DIV_RANGE] mplla_tx_clk_div,
	input [`DWC_E12MP_X4NS_TX_CLK_DIV_RANGE] mpllb_tx_clk_div,
`else
	input [1:0] mplla_tx_clk_div,
	input [1:0] mpllb_tx_clk_div,
`endif
	input [1:0] rx_pstate,
	input [1:0] rx_rate,
	input [1:0] rx_width,
	input [1:0] tx_pstate,
	input [1:0] tx_width,
	input [12:0] rx_vco_ld_val,
	input [15:0] cr_para_addr,
	input [15:0] cr_para_wr_data,
	input [15:0] sram_rd_data,
	input [19:0] tx_data,
`ifdef DWC_E12MP_X4NS_PMA
	input       mplla_ssc_clk_sel,
	input       mpllb_ssc_clk_sel,
	input       mplla_ssc_range,
	input       mpllb_ssc_range,
`else
	input [2:0] mplla_ssc_clk_sel,
	input [2:0] mpllb_ssc_clk_sel,
	input [2:0] mplla_ssc_range,
	input [2:0] mpllb_ssc_range,
`endif
	input [2:0] ref_range,
	input [2:0] rx_eq_att_lvl,
	input [2:0] rx_los_threshold,
	input [2:0] tx_rate,
	input [2:0] tx_vboost_lvl,
`ifdef DWC_E12MP_X4NS_PMA
	input [2:0] rx_eq_vga1_gain,
	input [2:0] rx_eq_vga2_gain,
	input [1:0] rx_eq_ctle_pole,
`else
	input [3:0] rx_eq_vga1_gain,
	input [3:0] rx_eq_vga2_gain,
	input [2:0] rx_eq_ctle_pole,
`endif
	input [3:0] rx_eq_afe_gain,
	input [3:0] tx_iboost_lvl,
	input [4:0] bs_rx_level,
	input [4:0] rx_eq_ctle_boost,
	input [4:0] rx_vref_ctrl,
`ifdef DWC_E12MP_X4NS_PMA
	input [6:0] rx_ref_ld_val,
`else
	input [5:0] rx_ref_ld_val,
`endif
	input [5:0] tx_eq_main,
	input [5:0] tx_eq_post,
	input [5:0] tx_eq_pre,
`ifdef DWC_C10_PMA
	input [`DWC_E12MP_X4NS_MPLL_DIV_MULT_RANGE] mplla_div_multiplier,
	input [`DWC_E12MP_X4NS_MPLL_DIV_MULT_RANGE] mpllb_div_multiplier,
`else
	input [6:0] mplla_div_multiplier,
	input [6:0] mpllb_div_multiplier,
`endif
	input [7:0] mplla_multiplier,
	input [7:0] mpllb_multiplier,
	input [7:0] rx_eq_dfe_tap1,
`ifdef DWC_C10_PMA
	input [`DWC_E12MP_X4NS_SSC_FRACN_CTRL_RANGE] mplla_fracn_ctrl,
	input [`DWC_E12MP_X4NS_SSC_FRACN_CTRL_RANGE] mpllb_fracn_ctrl,
`else
`ifdef DWC_E12MP_X4NS_PMA
	input [10:0] mplla_fracn_ctrl,
	input [10:0] mpllb_fracn_ctrl,
`else
	input [8:0] mplla_fracn_ctrl,
	input [8:0] mpllb_fracn_ctrl,
`endif
`endif
	input  ana_pwr_en,
	input  bs_acmode,
	input  bs_actest,
	input  bs_cdr,
	input  bs_ce,
	input  bs_rx_bigswing,
	input  bs_rx_init,
	input  bs_sdr,
	input  bs_tdi,
	input  bs_tx_lowswing,
	input  bs_udr,
	input  cr_para_clk,
	input  cr_para_rd_en,
	input  cr_para_sel,
	input  cr_para_wr_en,
	input  jtag_tck,
	input  jtag_tdi,
	input  jtag_tms,
	input  jtag_trst_n,
	input  lane_rx2tx_par_lb_en,
	input  lane_tx2rx_ser_lb_en,
	input  mplla_div10_clk_en,
	input  mplla_div16p5_clk_en,
	input  mplla_div8_clk_en,
	input  mplla_div_clk_en,
	input  mplla_force_en,
	input  mplla_init_cal_disable,
	input  mplla_ssc_en,
	input  mplla_state,
	input  mpllb_div10_clk_en,
	input  mpllb_div8_clk_en,
	input  mpllb_div_clk_en,
	input  mpllb_force_en,
	input  mpllb_init_cal_disable,
	input  mpllb_ssc_en,
	input  mpllb_state,
	input  pcs_pwr_stable,
	input  pg_mode_en,
	input  pg_reset,
	input  phy_reset,
 `ifdef DPALT 
	input  phy_typec_disable,
 `endif 
	input  pma_pwr_stable,
	input  ref_alt_clk_m,
	input  ref_alt_clk_p,
	input  ref_clk_div2_en,
	input  ref_clk_en,
	input  ref_clk_mplla_div2_en,
	input  ref_clk_mpllb_div2_en,
	input  ref_dig_clk,
	input  ref_pad_clk_m,
	input  ref_pad_clk_p,
	input  ref_repeat_clk_en,
	input  ref_use_pad,
	input  res_ack_in,
	input  res_req_in,
	input  rtune_req,
	input  rtune_ack,
	input  rx_adapt_afe_en,
	input  rx_adapt_cont,
	input  rx_adapt_dfe_en,
	input  rx_adapt_req,
	input  rx_adapt_ack,
	input  rx_align_en,
	input  rx_cdr_ssc_en,
	input  rx_cdr_track_en,
	input  rx_cdr_vco_lowfreq,
	input  rx_clk_shift,
	input  rx_data_en,
	input  rx_disable,
	input  rx_div16p5_clk_en,
	input  rx_invert,
	input  rx_los_lfps_en,
	input  rx_lpd,
	input  rx_offcan_cont,
	input  rx_req,
  input  rx_ack,
	input  rx_reset,
	input  rx_term_acdc,
	input  rx_term_en,
	input  scan_mode,
	input  scan_shift,
	input  scan_shift_cg,
	input  sram_bypass,
	input  sram_ext_ld_done,
	input  test_burnin,
	input  test_flyover_en,
	input  test_powerdown,
	input  test_stop_clk_en,
	input  test_tx_ref_clk_en,
	input  tx_ack,
	input  tx_beacon_en,
	input  tx_clk,
	input  tx_clk_rdy,
	input  tx_data_en,
	input  tx_detrx_req,
	input  tx_disable,
	input  tx_flyover_data_m,
	input  tx_flyover_data_p,
	input  tx_invert,
	input  tx_lpd,
	input  tx_master_mplla_state,
	input  tx_master_mpllb_state,
	input  tx_mpllb_sel,
	input  tx_mpll_en,
	input  tx_req,
	input  tx_reset,
	input  tx_vboost_en,
`ifdef DWC_E12MP_X4NS_PMA
	input [15:0] mplla_bandwidth,
	input [15:0] mpllb_bandwidth
`else
	input [`DWC_E12MP_X4NS_MPLL_BW_WIDTH-1:0] mplla_bandwidth,
	input [`DWC_E12MP_X4NS_MPLL_BW_WIDTH-1:0] mpllb_bandwidth
`endif
);

logic assertions_enabled;
logic lane_assertion_enabled;
logic power_up_mask;
logic isolate_en;
logic isolate_en_d;
logic test_mode;

logic all_assertions_dis;
logic tx2rx_ser_lb_en_assert_dis;
logic rx2tx_par_lb_en_assert_dis;
logic tx_vboost_en_assert_dis;
logic tx_data_en_assert_dis;
logic tx_req_assert_dis;
logic tx_pstate_assert_dis;
logic tx_lpd_assert_dis;
logic tx_rate_assert_dis;
logic tx_width_assert_dis;
logic tx_mpllb_sel_assert_dis;
logic tx_mpll_en_assert_dis;
logic tx_detrx_req_assert_dis;
logic tx_master_mplla_state_assert_dis;
logic tx_master_mpllb_state_assert_dis;
logic tx_eq_main_assert_dis;
logic tx_eq_post_assert_dis;
logic tx_eq_pre_assert_dis;
logic tx_reset_assert_dis;
logic tx_iboost_lvl_assert_dis;
logic tx_beacon_en_assert_dis;
logic tx_clk_rdy_assert_dis;
logic tx_disable_assert_dis;
logic tx_clk_assert_dis;
logic rx_align_en_assert_dis;
logic phy_reset_pwr_up_assert_dis;
logic pcs_pwr_stable_assert_dis;
logic rx_disable_assert_dis;

initial begin
   all_assertions_dis=1'b0;
   tx2rx_ser_lb_en_assert_dis=1'b0; 
   rx2tx_par_lb_en_assert_dis=1'b0;
   tx_vboost_en_assert_dis=1'b0;
   tx_data_en_assert_dis=1'b0;
   tx_req_assert_dis=1'b0;
   tx_pstate_assert_dis=1'b0;
   tx_lpd_assert_dis=1'b0;
   tx_rate_assert_dis=1'b0;
   tx_width_assert_dis=1'b0;
   tx_mpllb_sel_assert_dis=1'b0;
   tx_mpll_en_assert_dis=1'b0;
   tx_detrx_req_assert_dis=1'b0;
   tx_master_mplla_state_assert_dis=1'b0;
   tx_master_mpllb_state_assert_dis=1'b0;
   tx_eq_main_assert_dis=1'b0;
   tx_eq_post_assert_dis=1'b0;
   tx_eq_pre_assert_dis=1'b0;
   tx_reset_assert_dis=1'b0;
   tx_iboost_lvl_assert_dis=1'b0;
   tx_beacon_en_assert_dis=1'b0;
   tx_clk_rdy_assert_dis=1'b0;
   tx_disable_assert_dis=1'b0;
   tx_clk_assert_dis=1'b0;
   rx_align_en_assert_dis=1'b0;
   phy_reset_pwr_up_assert_dis=1'b0;
   pcs_pwr_stable_assert_dis=1'b0;
   isolate_en=1'b0;
   rx_disable_assert_dis=1'b0;
end

initial begin
  power_up_mask = 1'b1;
  wait (phy_reset === 1'b1);
  #10fs;
  power_up_mask = 1'b0;
end

assign test_mode = bs_ce | test_burnin | test_powerdown | scan_mode | scan_shift | scan_shift_cg;
assign assertions_enabled = ~power_up_mask & ~test_mode & ~all_assertions_dis;
assign lane_assertion_enabled = assertions_enabled & phy_reset===1'b0 & isolate_en!==1'b1 & isolate_en_d!==1'b1;
// Added a 1ps delay to isolate_en because in UPF mode, this signal is deasserted to 0 before
// the other signals toggle.
assign #1ps isolate_en_d = isolate_en;


//----------------------------------------------------------------------
// Lane assertions
//----------------------------------------------------------------------
  //----------------------------------------------------------------------
  // Local variables declaration
  //----------------------------------------------------------------------
  logic        phy_reset_exit;
  logic        tx_pg_reset_and_exit;
  logic        phy_reset_negedge;
  logic        curr_tx_mpll_en;
  logic        curr_tx_mpllb_sel;
  logic        curr_tx_lpd;
  logic        tx_detrx_handshake_active;
  logic [1:0]  prev_tx_width;
  logic        tx_clock_toggling;
  logic        tx_width_trans;
  logic        tx_req2ack;
  logic [10:0] tx_clk_count;
  logic        curr_rx_adapt_afe_en;
  logic [26:0] curr_rx_eq_bus;
  logic [26:0] rx_eq_bus;
  
  logic        tx_phy_reset_exit;
  logic        phy_or_tx_reset_negedge;
  logic        phy_or_tx_reset_negedge_to_tx_ack_negedge;
  logic        phy_or_tx_reset;
  logic [1:0]  curr_tx_pstate;
  logic        tx_in_P0;
  logic        tx_in_P0s;
  logic        tx_handshake_reset;
  logic        tx_handshake_req_active;
  logic        tx_handshake_active;
  
  logic       rx_phy_reset_exit;
  logic       rx_pg_reset_and_exit;
  logic       phy_or_rx_reset_negedge;
  logic       phy_or_rx_reset_negedge_to_rx_ack_negedge;
  logic       phy_or_rx_reset;
  logic [1:0] curr_rx_pstate;
  logic       rx_in_P0;
  logic       rx_in_P0s;
  logic       rx_in_P2;
  logic       rx_handshake_reset;
  logic       rx_handshake_req_active;
  logic       rx_adapt_req_active;
  logic       rx_handshake_active;

  initial begin
    phy_reset_negedge = 1'b0;
    curr_tx_mpll_en = 1'b0;
    curr_tx_mpllb_sel = 1'b0;
    curr_tx_lpd = 1'b0;
    curr_rx_adapt_afe_en = 1'b0;
    tx_detrx_handshake_active = 1'b0;
    tx_phy_reset_exit = 1'b0;
    phy_or_tx_reset_negedge = 1'b0;
    phy_or_tx_reset_negedge_to_tx_ack_negedge = 1'b0;
    curr_tx_pstate = 2'h0;
    tx_handshake_req_active = 1'b0;
    rx_phy_reset_exit = 1'b0;
    rx_pg_reset_and_exit = 1'b0;
    tx_pg_reset_and_exit = 1'b0;
    phy_or_rx_reset_negedge = 1'b0;
    phy_or_rx_reset_negedge_to_rx_ack_negedge = 1'b0;
    curr_rx_pstate = 2'h0;
    rx_handshake_req_active = 1'b0;
    rx_adapt_req_active = 0;
    prev_tx_width=0;
    tx_clock_toggling=0;
    tx_width_trans=0;
    tx_req2ack=0;
    tx_clk_count=0;
  end

  //----------------------------------------------------------------------
  // Logic Implementation
  //----------------------------------------------------------------------
  assign phy_reset_exit = rx_phy_reset_exit | tx_phy_reset_exit;

  always @(negedge phy_reset) begin
    phy_reset_negedge = 1'b1;
    #1ps;
    phy_reset_negedge = 1'b0;
  end

  // For tx
  assign tx_handshake_active = tx_handshake_reset | tx_handshake_req_active;
  assign tx_in_P0  = (curr_tx_pstate==`PSTATE_P0) & ~curr_tx_lpd & ~tx_handshake_req_active & ~tx_handshake_reset & ~phy_reset & ~tx_reset;
  assign tx_in_P0s = (curr_tx_pstate==`PSTATE_P0S) & ~tx_handshake_req_active & ~tx_handshake_reset & ~phy_reset & ~tx_reset; 

  always @(posedge pg_reset or negedge tx_ack) begin
    if (pg_reset)
      tx_pg_reset_and_exit = 1'b1;
    else if (!tx_ack)
      tx_pg_reset_and_exit = 1'b0;
  end
  
  always @(posedge phy_reset_negedge or negedge tx_ack) begin
    if (phy_reset_negedge)
      tx_phy_reset_exit = 1'b1;
    else if (!tx_ack)
      tx_phy_reset_exit = 1'b0;
  end

  always @(tx_ack) begin
    curr_tx_pstate = tx_pstate;
    curr_tx_mpll_en = tx_mpll_en;
    curr_tx_mpllb_sel = tx_mpllb_sel;
    curr_tx_lpd = tx_lpd;
  end

  assign phy_or_tx_reset = phy_reset | tx_reset;

  always @(negedge phy_or_tx_reset) begin
    phy_or_tx_reset_negedge = 1'b1;
    #1ps;
    phy_or_tx_reset_negedge = 1'b0;
  end

  always @(posedge phy_or_tx_reset_negedge or negedge tx_ack) begin
    if (phy_or_tx_reset_negedge)
      phy_or_tx_reset_negedge_to_tx_ack_negedge = 1'b1;
    else if (!tx_ack)
      phy_or_tx_reset_negedge_to_tx_ack_negedge = 1'b0;
  end

  assign tx_handshake_reset = phy_or_tx_reset ? 1'b0 : phy_or_tx_reset_negedge_to_tx_ack_negedge;

  always @(posedge tx_req or negedge tx_ack or posedge tx_handshake_reset or posedge phy_or_tx_reset) begin
    if (tx_handshake_reset | phy_or_tx_reset)
      tx_handshake_req_active = 1'b0;
    else if (tx_req)
      tx_handshake_req_active = 1'b1;
    else if (!tx_ack)
      tx_handshake_req_active = 1'b0;
  end

  always @(posedge tx_detrx_req or negedge tx_ack or posedge tx_handshake_reset or posedge phy_or_tx_reset) begin
    if (tx_handshake_reset | phy_or_tx_reset)
      tx_detrx_handshake_active = 1'b0;
    else if (tx_detrx_req)
      tx_detrx_handshake_active = 1'b1;
    else if (!tx_ack)
      tx_detrx_handshake_active = 1'b0;
  end
  
  always @ (tx_width)
   begin
      if(tx_width==1 && tx_width==0)
         tx_width_trans=1;
      prev_tx_width=tx_width;
   end
   always @ (posedge tx_req)
   begin 
      tx_req2ack=1;
      @ (posedge tx_ack)
      tx_req2ack=0;
      tx_width_trans=0;
   end
   always
   begin
      fork : tx_clk_fork
      begin
         @ (tx_clk)
	 tx_clock_toggling=1;
	 disable tx_clk_fork;
      end
      begin  
         `ifdef DWC_C8_PMA
	 #80
	 `else
	 # 30;
	 `endif
	 tx_clock_toggling=0;
	 disable tx_clk_fork;
      end 
      join   	 
   end
  
  //For rx
  assign rx_handshake_active = rx_handshake_reset | rx_handshake_req_active;
  assign rx_in_P0  = (curr_rx_pstate==`PSTATE_P0) & ~rx_handshake_req_active & ~rx_handshake_reset & ~phy_reset & ~rx_reset;
  assign rx_in_P0s = (curr_rx_pstate==`PSTATE_P0S) & ~rx_handshake_req_active & ~rx_handshake_reset & ~phy_reset & ~rx_reset; 
  assign rx_in_P2 = (curr_rx_pstate==`PSTATE_P2) & ~rx_handshake_req_active & ~rx_handshake_reset & ~phy_reset & ~rx_reset; 

  always @(posedge pg_reset or negedge rx_ack) begin
    if (pg_reset)
      rx_pg_reset_and_exit = 1'b1;
    else if (!rx_ack)
      rx_pg_reset_and_exit = 1'b0;
  end

  always @(posedge phy_reset_negedge or negedge rx_ack) begin
    if (phy_reset_negedge)
      rx_phy_reset_exit = 1'b1;
    else if (!rx_ack)
      rx_phy_reset_exit = 1'b0;
  end

  always @(rx_ack) begin
    curr_rx_pstate = rx_pstate;
    curr_rx_adapt_afe_en = rx_adapt_afe_en;
`ifdef DWC_C10_PMA
    curr_rx_eq_bus = {rx_eq_att_lvl, rx_eq_ctle_boost, 3'b000, 
                      rx_eq_dfe_tap1, rx_eq_afe_gain, 4'b0000};
`else
    curr_rx_eq_bus = {rx_eq_att_lvl, rx_eq_ctle_boost, rx_eq_ctle_pole, 
                      rx_eq_dfe_tap1, rx_eq_vga1_gain, rx_eq_vga2_gain};
`endif
  end

`ifdef DWC_C10_PMA
  assign rx_eq_bus = {rx_eq_att_lvl, rx_eq_ctle_boost, 3'b000, 
                      rx_eq_dfe_tap1, rx_eq_afe_gain, 4'b0000};
`else
  assign rx_eq_bus = {rx_eq_att_lvl, rx_eq_ctle_boost, rx_eq_ctle_pole, 
                      rx_eq_dfe_tap1, rx_eq_vga1_gain, rx_eq_vga2_gain};
`endif

  assign phy_or_rx_reset = phy_reset | rx_reset;

  always @(negedge phy_or_rx_reset) begin
    phy_or_rx_reset_negedge = 1'b1;
    #1ps;
    phy_or_rx_reset_negedge = 1'b0;
  end

  always @(posedge phy_or_rx_reset_negedge or negedge rx_ack) begin
    if (phy_or_rx_reset_negedge)
      phy_or_rx_reset_negedge_to_rx_ack_negedge = 1'b1;
    else if (!rx_ack)
      phy_or_rx_reset_negedge_to_rx_ack_negedge = 1'b0;
  end

  logic rx_handshake_reset_d;
  assign rx_handshake_reset = phy_or_rx_reset ? 1'b0 : phy_or_rx_reset_negedge_to_rx_ack_negedge;
  assign #1ps rx_handshake_reset_d = rx_handshake_reset;

  always @(posedge rx_req or negedge rx_ack or posedge rx_handshake_reset or posedge phy_or_rx_reset) begin
    if (rx_handshake_reset | phy_or_rx_reset)
      rx_handshake_req_active = 1'b0;
    else if (rx_req)
      rx_handshake_req_active = 1'b1;
    else if (!rx_ack)
      rx_handshake_req_active = 1'b0;
  end
  
  always @(posedge rx_adapt_req or negedge rx_adapt_ack or posedge rx_handshake_reset) begin
    if (rx_handshake_reset)
      rx_adapt_req_active = 1'b0;
    else if (rx_adapt_req)
      rx_adapt_req_active = 1'b1;
    else if (!rx_adapt_ack)
      rx_adapt_req_active = 1'b0;
  end
  
  //----------------------------------------------------------------------
  // Assertion Implementation
  //---------------------------------------------------------------------- 

  // For TX
  
  // tx_clk When tx_in_P0===1 check rising edge of tx_clk to rising_edge of tx_ana_dword_clk is minimum 1/2 of the fastest tx_clk
  /*
  always @(posedge tx_clk)
   begin
      if(lane_assertion_enabled && tx_width==0 && tx_clk_count<2)
      begin
         #1ps;
	 fork : ana_dword_clk_fork
	 begin
	    @ (negedge tx_clk)
	    disable ana_dword_clk_fork; 
	 end
	 begin
	   @ (posedge scan_tx_ana_dword_clk)
	   tx_clk_count=tx_clk_count+1;
	   assert (1==0); 
	   disable ana_dword_clk_fork;
	 end
	 join             
      end	    
   end
   */
  
  // tx_reset no rising edge during tx_phy_reset exit  
  always @(posedge tx_reset)
   begin
      if(lane_assertion_enabled & ~tx_reset_assert_dis)
      begin
         #1ps;
         assert (tx_phy_reset_exit==0);    
      end	    
   end
   
   // tx_reset Minimum assertion time (rising edge to falling edge) = 10ns
   always @(posedge tx_reset)
   begin
      if(lane_assertion_enabled & ~tx_reset_assert_dis)
      begin
         fork : tx_reset_fork
         begin
            @ (negedge tx_reset)
	    min_tx_reset_time : assert (1==0); 
	    disable tx_reset_fork;
	 end   
	 begin
	    #10ns;
            disable tx_reset_fork;     
         end
      join
      end	    
   end
   
   // txX_iboost_lvl must be stable when !(phy_reset | tx_reset)
   always @(tx_iboost_lvl)
   if(lane_assertion_enabled & ~tx_iboost_lvl_assert_dis)
   begin
      tx_iboost_lvl_assert : assert (phy_reset | tx_reset | isolate_en_d);  
   end
   
    // tx_beacon_en no rising edge during tx_phy_reset exit
   always @ (posedge tx_beacon_en)
   if(lane_assertion_enabled & ~tx_beacon_en_assert_dis)
   begin
      assert (tx_phy_reset_exit==0);
   end   
  
  // laneX_tx2rx_ser_lb_en Must be 0    
  always @(*)
   if(lane_assertion_enabled & ~tx2rx_ser_lb_en_assert_dis)   
   begin    
      #1ns;
      tx2rx_ser_lb_en_assert : assert (lane_tx2rx_ser_lb_en == 0); 
   end
   
   //lanex_rx2tx_par_lb_en Must be 0
  always @(*)
   if(lane_assertion_enabled & ~rx2tx_par_lb_en_assert_dis)   
   begin    
      #1ns;
      rx2tx_par_lb_en_assert : assert (lane_rx2tx_par_lb_en == 0); 
   end  
   
  // tx_vboost_en must be stable when !(phy_reset | tx_reset)    
  always @(tx_vboost_en)
   if(lane_assertion_enabled &~tx_vboost_en_assert_dis)   
   begin    
      tx_vboost_en_assert : assert (phy_reset | tx_reset | isolate_en_d); 
   end 
   
  // tx_clk_rdy When switching from 16/20bit to 8/10bit mode, tx_clk_rdy=0 between tx_req=1 and tx_ack=1 
  always @(*)
   if(lane_assertion_enabled & ~tx_clk_rdy_assert_dis)   
   begin    
      #1ps;
      if(tx_width_trans==1 && tx_req2ack==1)    
         assert(tx_clk_rdy==0); 
   end 
   
   // tx_disable tx_disable=0  when (tx_in_P0 | tx_in_P0s | rxdet_req=1 | tx_beacon_en=1 | tx_phy_reset exit)
  always @(*)
   if(lane_assertion_enabled & ~tx_disable_assert_dis)   
   begin    
      #1ps;
   `ifdef DPALT 
      if((tx_in_P0==1 || tx_in_P0s==1 || tx_detrx_req==1 || tx_beacon_en==1) && tx_phy_reset_exit==1)
   `else 
      if((tx_in_P0==1) || (tx_in_P0s==1) || (tx_phy_reset_exit==1) || (tx_detrx_req==1) || (tx_beacon_en==1))
   `endif 
         assert(tx_disable==0);	
   end 
  
   //  ((tx_in_P0) | (tx_in_P0S ) |(txX_data_en===1) | ((txX_pstate===P0 | txX_pstate===P0S) & tx_handshake_active) and tx_mplla/b_master_state=1 and mplla/b_state=1, the clock must be toggling
  always @(*)
   if(lane_assertion_enabled & ~tx_clk_assert_dis)   
   begin    
      #1ps;
      if((tx_in_P0==1 || tx_in_P0s==1 || tx_data_en===1 || ((tx_pstate<2) && (tx_handshake_active==1))) && tx_master_mplla_state==1 && tx_master_mpllb_state==1 && mplla_state==1 && mpllb_state==1 )
      begin
         assert (tx_clock_toggling==1);	 
      end	 
   end 
  
  // tx_clk_rdy In 8/10/16/20bit mode, tx_clk_rdy=1 when tx_pstate=P0/P0s and tx_mplla/b_master_state=1 and mplla/b_state=1
  always @(*)
   if(lane_assertion_enabled & ~tx_clk_rdy_assert_dis)   
   begin    
      #1ps;
      if((tx_in_P0==1  || tx_in_P0s==1 ) && tx_master_mplla_state==1 && tx_master_mpllb_state==1 && mplla_state==1 && mpllb_state==1 )
      begin       
	 if(tx_width<2)	 
	    assert (tx_clk_rdy==1); 	   
      end	 
   end 
   

  // tx_data_en Must be 0 when !tx_in_P0 or tx_lpd===1
  always @(*) begin
    #1ps;
    if (!tx_data_en_assert_dis && lane_assertion_enabled && ((tx_in_P0===1'b0) || (curr_tx_lpd===1'b1))) begin
      tx_data_en_assert: 
        assert (tx_data_en == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_data_en Must be 0 when !tx_in_P0 or tx_lpd===1 violation!");
    end
  end

  // tx_req no rising edge when tx_ack===1
  always @(posedge tx_req iff (!tx_req_assert_dis && lane_assertion_enabled)) begin
    #1ps;
    tx_req_posedge_assert: 
      assert (tx_ack!==1'b1);
      //else $display("PHY_INF_ASSERTION_ERROR: tx_req no rising edge when tx_ack===1 violation!");
  end
  
  // tx_req no falling edge when tx_ack===0
  always @(negedge tx_req iff (!tx_req_assert_dis && lane_assertion_enabled)) begin
    #1ps;
    tx_req_negedge_assert: 
      assert (tx_ack!==1'b0);
      //else $display("PHY_INF_ASSERTION_ERROR: tx_req no falling edge when tx_ack===0 violation!");
  end
  
  // tx_req must be 0 when ref_clk_en===0 or phy_reset===1 or tx_reset===1 or tx_handshake_reset===1'b1 or tx_detrx_handshake_active===1'b1
  always @(*) begin
    #1ps;
    if (!tx_req_assert_dis && lane_assertion_enabled && ((ref_clk_en===1'b0) || (phy_reset===1'b1) || (tx_reset===1'b1) 
                                                         || (tx_handshake_reset===1'b1) || (tx_detrx_handshake_active===1'b1))) begin
      tx_req_assert: 
        assert (tx_req == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_req must be 0 when ref_clk_en===0 or phy_reset===1 or tx_reset===1 or tx_handshake_reset===1'b1 or tx_detrx_handshake_active===1'b1 violation!");
    end
  end

  // tx_pstate must not be 2'b00 (P0) or 2'b01 (P0s) when (tx_disable===1  | ref_clk_en===0)
  always @(*) begin
    #1ps;
    if (!tx_pstate_assert_dis && lane_assertion_enabled && (tx_disable===1'b1 || ref_clk_en===1'b0)) begin
      tx_pstate_assert: 
        assert ((tx_pstate !== `PSTATE_P0) && (tx_pstate !== `PSTATE_P0S));
        //else $display("PHY_INF_ASSERTION_ERROR: tx_pstate must not be 2'b00 (P0) or 2'b01 (P0s) when (tx_disable===1  | ref_clk_en===0) violation!");
    end
  end
  
  // tx_pstate must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_pstate_stable_assert: 
    assert property (@(tx_pstate) disable iff (tx_pstate_assert_dis || !lane_assertion_enabled)
     (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_pstate must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");
  
  // tx_lpd must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_lpd_stable_assert: 
    assert property (@(tx_lpd) disable iff (tx_lpd_assert_dis || !lane_assertion_enabled)
      (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_lpd must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");
  
  // tx_rate must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_rate_stable_assert: 
    assert property (@(tx_rate) disable iff (tx_rate_assert_dis || !lane_assertion_enabled)
      (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_rate must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");

`ifdef DWC_C10_PMA
  // tx_rate!==3'b100 && tx_rate!==3'b101 && tx_rate!==3'b110 && tx_rate!==3'b111
  tx_rate_illegal_assert: 
    assert property (@(tx_rate) disable iff (tx_rate_assert_dis || !lane_assertion_enabled)
      (tx_rate!==3'b100 && tx_rate!==3'b101 && tx_rate!==3'b110 && tx_rate!==3'b111));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_rate=%0h illegal states found!", tx_rate);
`else // DWC_E12_PMA
  // tx_rate!==3'b100 && tx_rate!==3'b101
  tx_rate_illegal_assert: 
    assert property (@(tx_rate) disable iff (tx_rate_assert_dis || !lane_assertion_enabled)
      (tx_rate!==3'b100 && tx_rate!==3'b101));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_rate=%0h illegal states found!", tx_rate);
`endif

  // tx_width must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_width_stable_assert: 
    assert property (@(tx_width) disable iff (tx_width_assert_dis || !lane_assertion_enabled)
      (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_width must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");
 
`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  // tx_mpllb_sel must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_mpllb_sel_stable_assert: 
    assert property (@(tx_mpllb_sel) disable iff (tx_mpllb_sel_assert_dis || !lane_assertion_enabled)
      (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_mpllb_sel must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");
`endif

  // tx_mpll_en must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1
  tx_mpll_en_stable_assert: 
    assert property (@(tx_mpll_en) disable iff (tx_mpll_en_assert_dis || !lane_assertion_enabled)
      (tx_handshake_req_active!==1'b1) && (tx_handshake_reset!==1'b1));
    //else $display("PHY_INF_ASSERTION_ERROR: tx_mpll_en must be stable when tx_handshake_req_active===1 or tx_handshake_reset===1 violation!");
  
  // tx_mpll_en must be 0 when (ref_clk_en===0 && tx_handshake_active===1)
  always @(*) begin
    #1ps;
    if (!tx_mpll_en_assert_dis && lane_assertion_enabled && ref_clk_en===1'b0 && tx_handshake_req_active===1'b1) begin
      tx_mpll_en_low_assert: 
        assert (tx_mpll_en == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_mpll_en must be 0 when (ref_clk_en===0 && tx_handshake_active===1) violation!");
    end
  end

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  // tx_mpll_en must be 1 (in_P0 or in_P0s)
  always @(*) begin
    #1ps;
    if (!tx_mpll_en_assert_dis && lane_assertion_enabled 
        && (tx_pstate==`PSTATE_P0 || tx_pstate==`PSTATE_P0S) 
        && tx_handshake_req_active===1'b1) begin
      tx_mpll_en_high_assert: 
        assert (tx_mpll_en == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_mpll_en must be 1 (in_P0 or in_P0s) violation!");
    end
  end
`endif  

  // tx_master_mplla_state must be 1 when (tx_in_P0 | tx_in_P0S) & (txX_mpllb_sel == 0)
  always @(*) begin
    #1ps;
    if (!tx_master_mplla_state_assert_dis && lane_assertion_enabled && (tx_in_P0===1'b1 || tx_in_P0s===1'b1) && (curr_tx_mpllb_sel===1'b0)) begin
      tx_master_mplla_state_assert: 
        assert (tx_master_mplla_state == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_master_mplla_state must be 1 when (tx_in_P0 | tx_in_P0S) & (txX_mpllb_sel == 0) violation!");
    end
  end

  // tx_master_mpllb_state must be 1 when (tx_in_P0 | tx_in_P0S) & (txX_mpllb_sel == 0)
  always @(*) begin
    #1ps;
    if (!tx_master_mpllb_state_assert_dis && lane_assertion_enabled && (tx_in_P0===1'b1 || tx_in_P0s===1'b1) && (curr_tx_mpllb_sel===1'b1)) begin
      tx_master_mpllb_state_assert: 
        assert (tx_master_mpllb_state == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_master_mpllb_state must be 1 when (tx_in_P0 | tx_in_P0S) & (txX_mpllb_sel == 0) violation!");
    end
  end

  // tx_detrx_req must be 0 if  (tx_in_P0 | tx_in_P0s | ref_clk_en == 0 | tx_handshake_req_active | tx_handshake_reset | phy_reset | tx_reset)
  always @(*) begin
    #1ps;
    if (!tx_detrx_req_assert_dis && lane_assertion_enabled 
        && ((ref_clk_en===1'b0) || (phy_reset===1'b1) || (tx_reset===1'b1) 
            || (tx_handshake_reset===1'b1) || (tx_handshake_req_active===1'b1) || (tx_in_P0===1'b1) || (tx_in_P0s===1'b1))) begin
      tx_detrx_req_assert: 
        assert (tx_detrx_req == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: tx_detrx_req must be 0 if  (tx_in_P0 | tx_in_P0s | ref_clk_en == 0 | tx_handshake_req_active | tx_handshake_reset | phy_reset | tx_reset) violation!");
    end
  end

  logic [7:0] tx_eq_sum;
  assign tx_eq_sum = tx_eq_main + tx_eq_post[5:2] + tx_eq_pre[5:2];
  
  bit dis_after_err_tx_eq_pre_ls_2bit_assert;
  initial dis_after_err_tx_eq_pre_ls_2bit_assert = 1'b0;

  // (@posedge txX_clk)  txX_eq_pre[1:0] must be 00
  tx_eq_pre_ls_2bit_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_pre_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_pre_ls_2bit_assert)
      (tx_eq_pre[1:0] == 2'b00))
    else dis_after_err_tx_eq_pre_ls_2bit_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: (@posedge txX_clk)  txX_eq_pre[1:0] must be 00 violation!");

  bit dis_after_err_tx_eq_post_ls_2bit_assert;
  initial dis_after_err_tx_eq_post_ls_2bit_assert = 1'b0;

`ifdef DWC_C10_PMA
  // (@posedge txX_clk)  txX_eq_post[1:0] must be 00 if tx_in_P0
  tx_eq_post_ls_2bit_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_post_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_post_ls_2bit_assert)
      tx_in_P0 |-> (tx_eq_post[1:0] == 2'b00))
      else dis_after_err_tx_eq_post_ls_2bit_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: (@posedge txX_clk)  txX_eq_post[1:0] must be 00 if tx_in_P0 violation!");
`else //E12
  // (@posedge txX_clk)  txX_eq_post[1:0] must be 00 or 10 if tx_in_P0
  tx_eq_post_ls_2bit_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_post_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_post_ls_2bit_assert)
      tx_in_P0 |-> (tx_eq_post[1:0] == 2'b00 || tx_eq_post[1:0] == 2'b10))
      else dis_after_err_tx_eq_post_ls_2bit_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: (@posedge txX_clk)  txX_eq_post[1:0] must be 00 or 10 if tx_in_P0 violation!");
`endif

  bit dis_after_err_tx_eq_main_assert;
  bit dis_after_err_tx_eq_sum_assert;
  bit dis_after_err_tx_eq_pre_assert;
  bit dis_after_err_tx_eq_post_assert;
  initial begin
    dis_after_err_tx_eq_main_assert = 1'b0;
    dis_after_err_tx_eq_sum_assert = 1'b0;
    dis_after_err_tx_eq_pre_assert = 1'b0;
    dis_after_err_tx_eq_post_assert = 1'b0;
  end

`ifdef DWC_C10_PMA
  // tx_eq_main @(posedge txX_clk) must be >0 and <=24 if tx_in_P0
  tx_eq_main_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_main_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_main_assert)
      tx_in_P0 |-> (tx_eq_main > 0 && tx_eq_main <= 24))
    else dis_after_err_tx_eq_main_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_main @(posedge txX_clk) must be >0 and <=24 if tx_in_P0 violation!");

  // (@posedge txX_clk) [txX_eq_main[5:0] + txX_eq_pre[5:2] + txX_eq_post[5:2]] <= 24 if tx_in_P0
  tx_eq_sum_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_main_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_sum_assert)
      tx_in_P0 |-> (tx_eq_sum > 0 && tx_eq_sum <= 24))
    else dis_after_err_tx_eq_sum_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: (@posedge txX_clk) [txX_eq_main[5:0] + txX_eq_pre[5:2] + txX_eq_post[5:2]] <= 24 if tx_in_P0 violation!");

  // tx_eq_pre (@posedge txX_clk) must be >=0 and <=24 if {tx_in_P0}
  tx_eq_pre_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_pre_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_pre_assert)
      tx_in_P0 |-> (tx_eq_pre >= 0 && tx_eq_pre <= 24))
    else dis_after_err_tx_eq_pre_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_pre (@posedge txX_clk) must be >=0 and <=24 if {tx_in_P0} violation!");

  // tx_eq_post (@posedge txX_clk) must be >=0 and <=32 if {tx_in_P0}
  tx_eq_post_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_post_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_post_assert)
      tx_in_P0 |-> (tx_eq_post >= 0 && tx_eq_post <= 32))
    else dis_after_err_tx_eq_post_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_post (@posedge txX_clk) must be >=0 and <=32 if {tx_in_P0} violation!");
`else //E12
  // tx_eq_main @(posedge txX_clk) must be >0 and <=40 if tx_in_P0
  tx_eq_main_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_main_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_main_assert)
      tx_in_P0 |-> (tx_eq_main > 0 && tx_eq_main <= 40))
    else dis_after_err_tx_eq_main_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_main @(posedge txX_clk) must be >0 and <=40 if tx_in_P0 violation!");
  
  // (@posedge txX_clk) [txX_eq_main[5:0] + txX_eq_pre[5:2] + txX_eq_post[5:2]] <= 40 if tx_in_P0
  tx_eq_sum_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_main_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_sum_assert)
      tx_in_P0 |-> (tx_eq_sum > 0 && tx_eq_sum <= 40))
    else dis_after_err_tx_eq_sum_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: (@posedge txX_clk) [txX_eq_main[5:0] + txX_eq_pre[5:2] + txX_eq_post[5:2]] <= 40 if tx_in_P0 violation!");

  // tx_eq_pre (@posedge txX_clk) must be >=0 and <=40 if {tx_in_P0}
  tx_eq_pre_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_pre_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_pre_assert)
      tx_in_P0 |-> (tx_eq_pre >= 0 && tx_eq_pre <= 40))
    else dis_after_err_tx_eq_pre_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_pre (@posedge txX_clk) must be >=0 and <=40 if {tx_in_P0} violation!");

  // tx_eq_post (@posedge txX_clk) must be >=0 and <=60 if {tx_in_P0}
  tx_eq_post_assert:
    assert property (@(posedge tx_clk) disable iff (tx_eq_post_assert_dis || !lane_assertion_enabled || dis_after_err_tx_eq_post_assert)
      tx_in_P0 |-> (tx_eq_post >= 0 && tx_eq_post <= 60))
    else dis_after_err_tx_eq_post_assert = 1'b1;
    //else $display("PHY_INF_ASSERTION_ERROR: tx_eq_post (@posedge txX_clk) must be >=0 and <=60 if {tx_in_P0} violation!");
`endif


  // For RX
   always @(posedge rx_reset)
   begin
      if(lane_assertion_enabled)
      begin  
         #1ps;      
         assert (rx_phy_reset_exit==0);
        // else $display("error posedge of rx_reset during initial condition");  
      end	 
   end

`ifndef DWC_SHORT_RX_RESET
   always @(posedge rx_reset)
   begin
      if(lane_assertion_enabled)
      begin
         fork : rx_reset_fork
         begin
            @ (negedge rx_reset)
	          min_rx_reset_time : assert (1==0); 
	          disable rx_reset_fork;
	  end   
	  begin 
                #2;
                disable rx_reset_fork;     
          end
         join
      end	    
   end
`endif
   
   always @(*)
   if(lane_assertion_enabled &~rx_align_en_assert_dis)   
   begin    
      #1ps;
      if(!(phy_reset | rx_reset))    
         assert(rx_align_en==0);	 
   end 
   
   always @(rx_vref_ctrl)
   if(lane_assertion_enabled)   
   begin    
      assert(phy_reset | rx_reset | isolate_en_d);       	 
   end 
   
   always @(*)
   if(lane_assertion_enabled)   
   begin    
      #1ps;
      if(!(phy_reset | rx_reset))    
         assert(rx_clk_shift==0);	 
   end 

`ifdef DWC_C10_PMA
   always @(*)
   if(lane_assertion_enabled && ~rx_disable_assert_dis)
   begin    
      #1ps;
   `ifdef DPALT 
      if(rx_in_P0==1 || rx_in_P0s==1 || (rx_pstate<3 && (rx_handshake_req_active==1 || rx_handshake_reset==1) && rx_phy_reset_exit==1))    
   `else 
      if(rx_in_P0==1 || rx_in_P0s==1 || rx_phy_reset_exit==1 || (rx_pstate<3 && (rx_handshake_req_active==1 || rx_handshake_reset==1)))    
   `endif 
         assert(rx_disable==0);	 
   end 
   always @(*)
   if(lane_assertion_enabled)   
   begin    
      #2ns; // for gate delay
   `ifdef DPALT 
      if(!(phy_reset | rx_reset | rx_in_P2 | rx_pg_reset_and_exit | phy_typec_disable))    
   `else 
      if(!(phy_reset | rx_reset | rx_in_P2 | rx_pg_reset_and_exit))    
   `endif 
        rx_term_en_assert:  
         assert(rx_term_en==1);	 
   end
`else  
   always @(*)
   if(lane_assertion_enabled && ~rx_disable_assert_dis) 
   begin    
      #1ps;
      if(rx_in_P0==1 || rx_in_P0s==1 || rx_phy_reset_exit==1 || (rx_pstate<2 && (rx_handshake_req_active==1 || rx_handshake_reset==1)))    
         assert(rx_disable==0);	 
   end 
   always @(*)
   if(lane_assertion_enabled)   
   begin    
      #2ns; // for gate delay
      if(!(phy_reset | rx_reset | rx_pg_reset_and_exit)) begin 
        rx_term_en_assert:  
          assert(rx_term_en==1);	 
      end
   end
`endif

   always @(*)
   if(lane_assertion_enabled)   
   begin    
      #1ps;
      if(rx_data_en==1 && rx_pstate==0)    
         assert(rx_clk_shift==0);	 
   end 
     
   logic phy_rx_reset_d, phy_rx_reset_extended;
   assign #1ps phy_rx_reset_d = phy_reset | rx_reset;
   assign phy_rx_reset_extended = phy_reset | rx_reset | phy_rx_reset_d;

   always @(rx_los_lfps_en)
   if(lane_assertion_enabled)   
   begin    
      assert (phy_rx_reset_extended);
   end 

   always @(rx_los_threshold)
   if(lane_assertion_enabled)   
   begin    
    rx_los_threshold_assert : 
      assert (phy_rx_reset_extended);
   end

  
  logic rx_handshake_req_active_d, rx_handshake_req_active_shaped;
  assign #1ps rx_handshake_req_active_d = (rx_handshake_req_active===1'b1);
  assign rx_handshake_req_active_shaped = ~(rx_handshake_req_active_d ^ rx_handshake_req_active) & rx_handshake_req_active_d;

  always @ (rx_pstate)
     if(lane_assertion_enabled)
     begin
        rx_pstate_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end
  always @ (rx_lpd)
     if(lane_assertion_enabled)
     begin
        rx_lpd_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end   
  always @ (rx_rate)
     if(lane_assertion_enabled)
     begin
        rx_rate_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end   
  always @ (rx_width)
     if(lane_assertion_enabled)
     begin
        rx_width_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end     
  always @ (rx_adapt_afe_en)
     if(lane_assertion_enabled)
     begin
        rx_adapt_afe_en_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end  
  always @ (rx_adapt_dfe_en)
     if(lane_assertion_enabled)
     begin
        rx_adapt_dfe_en_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end     
  always @ (rx_eq_att_lvl)
     if(lane_assertion_enabled)
     begin
       rx_eq_att_lvl_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end    
`ifdef DWC_C10_PMA
  always @ (rx_eq_afe_gain)
     if(lane_assertion_enabled)
     begin
        assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end
`else
  always @ (rx_eq_vga1_gain)
     if(lane_assertion_enabled)
     begin
        rx_eq_vga1_gain_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end     
  always @ (rx_eq_vga2_gain)
     if(lane_assertion_enabled)
     begin
        rx_eq_vga2_gain_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end
  always @ (rx_eq_ctle_pole)
     if(lane_assertion_enabled)
     begin
        rx_eq_ctle_pole_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end   
`endif
  always @ (rx_eq_ctle_boost)
     if(lane_assertion_enabled)
     begin
       rx_eq_ctle_boost_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end 
  always @ (rx_eq_dfe_tap1)
     if(lane_assertion_enabled)
     begin
        rx_eq_dfe_tap1_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_handshake_reset_d===1 | rx_adapt_req_active===1));
     end   
  always @ (rx_cdr_vco_lowfreq)
     if(lane_assertion_enabled)
     begin
        rx_cdr_vco_lowfreq_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_adapt_req_active===1));
     end    
  always @ (rx_ref_ld_val)
     if(lane_assertion_enabled)
     begin
        rx_ref_ld_val_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_adapt_req_active===1));
     end  
  always @ (rx_vco_ld_val)
     if(lane_assertion_enabled)
     begin
        rx_vco_ld_val_wrt_rx_handshake_req : assert(!(rx_handshake_req_active_shaped===1 | rx_adapt_req_active===1));
     end


  rx_cdr_ssc_en_stable_assert: 
    assert property (@(rx_cdr_ssc_en) disable iff (!lane_assertion_enabled)
      (phy_reset | rx_reset | isolate_en));
    //else $display("PHY_INF_ASSERTION_ERROR: rx_cdr_ssc_en Must be stable when !(phy_reset | rx_reset) violation!");

`ifdef DWC_C10_PMA
  rx_cdr_vco_lowfreq_assert: 
    assert property (@(rx_cdr_vco_lowfreq) disable iff (!lane_assertion_enabled)
      (phy_reset | rx_reset));
    //else $display("PHY_INF_ASSERTION_ERROR: rx_cdr_vco_lowfreq Must be stable when !(phy_reset | rx_reset) violation!");
`elsif DWC_C8_PMA
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !((phy_reset===1'b1) || (rx_reset===1'b1))) begin
      rx_cdr_vco_lowfreq_assert: 
        assert (rx_cdr_vco_lowfreq == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_cdr_vco_lowfreq Must be 0 when !(phy_reset | rx_reset) violation!");
    end
  end
`else //E12
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !((phy_reset===1'b1) || (rx_reset===1'b1))) begin
      rx_cdr_vco_lowfreq_assert: 
        assert (rx_cdr_vco_lowfreq == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_cdr_vco_lowfreq Must be 1 when !(phy_reset | rx_reset) violation!");
    end
  end
`endif

  rx_ref_ld_val_stable_assert: 
    assert property (@(rx_ref_ld_val) disable iff (!lane_assertion_enabled)
      rx_handshake_req_active!==1'b1);
    //else $display("PHY_INF_ASSERTION_ERROR: rx_ref_ld_val must be stable when rx_handshake_req_active===1 violation!");

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (rx_handshake_req_active===1)) begin
      rx_ref_ld_val_assert: 
        assert (rx_ref_ld_val != 6'h0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_ref_ld_val must be non-zero when rx_handshake_req_active===1 violation!");
    end
  end

  rx_vco_ld_val_stable_assert: 
    assert property (@(rx_vco_ld_val) disable iff (!lane_assertion_enabled)
      rx_handshake_req_active!==1'b1);
    //else $display("PHY_INF_ASSERTION_ERROR: rx_vco_ld_val must be stable when rx_handshake_req_active===1 violation!");

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (rx_handshake_req_active===1)) begin
      rx_vco_ld_val_assert: 
        assert (rx_vco_ld_val != 13'h0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_vco_ld_val must be non-zero when rx_handshake_req_active===1 violation!");
    end
  end

`ifdef DWC_C10_PMA
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !((phy_reset===1'b1) || (rx_reset===1'b1))) begin
      rx_term_acdc_assert: 
        assert (rx_term_acdc == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_term_acdc Must be 1 when !(phy_reset | rx_reset) violation!");
    end
  end
`elsif DWC_C8_PMA
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !((phy_reset===1'b1) || (rx_reset===1'b1))) begin
      rx_term_acdc_assert: 
        assert (rx_term_acdc == 1'b1);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_term_acdc Must be 1 when !(phy_reset | rx_reset) violation!");
    end
  end
`else //E12
  rx_term_acdc_assert: 
    assert property (@(rx_term_acdc) disable iff (!lane_assertion_enabled)
      (phy_reset | rx_reset));
    //else $display("PHY_INF_ASSERTION_ERROR: rx_term_acdc Must be stable when !(phy_reset | rx_reset) violation!");
`endif

`ifdef DWC_C10_PMA
`elsif DWC_C8_PMA
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !((phy_reset===1'b1) || (rx_reset===1'b1))) begin
      rx_div16p5_clk_en_assert: 
        assert (rx_div16p5_clk_en == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_div16p5_clk_en Must be 0 when !(phy_reset | rx_reset) violation!");
    end
  end
`else //E12
  rx_div16p5_clk_en_assert: 
    assert property (@(rx_div16p5_clk_en) disable iff (!lane_assertion_enabled)
      !rx_in_P0);
    //else $display("PHY_INF_ASSERTION_ERROR: rx_div16p5_clk_en Must be stable when rx_in_P0!");
`endif

  always @(posedge rx_req iff (lane_assertion_enabled)) begin
    #1ps;
    rx_req_posedge_assert: 
      assert (rx_ack!==1'b1);
      //else $display("PHY_INF_ASSERTION_ERROR: rx_req no rising edge when rx_ack===1 violation!");
  end
  
  always @(negedge rx_req iff (lane_assertion_enabled)) begin
    #1ps;
    rx_req_negedge_assert: 
      assert (rx_ack!==1'b0);
      //else $display("PHY_INF_ASSERTION_ERROR: rx_req no falling edge when rx_ack===0 violation!");
  end
  
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && ((ref_clk_en===1'b0) || (phy_reset===1'b1) || (rx_reset===1'b1) || (rx_handshake_reset===1'b1))) begin
      rx_req_assert: 
        assert (rx_req == 1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_req must be 0 when ref_clk_en===0 or phy_reset===1 or rx_reset===1 or rx_handshake_reset===1'b1 violation!");
    end
  end

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (rx_disable===1'b1 || ref_clk_en===1'b0)) begin
      rx_pstate_assert: 
        assert ((rx_pstate !== `PSTATE_P0) && (rx_pstate !== `PSTATE_P0S));
        //else $display("PHY_INF_ASSERTION_ERROR: rx_pstate must not be 2'b00 (P0) or 2'b01 (P0s) when (rx_disable===1  | ref_clk_en===0) violation!");
    end
  end

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && !(rx_in_P0 || rx_reset || ((rx_handshake_req_active || rx_handshake_reset) && rx_pstate===2'b00))) begin
      rx_data_en_assert: 
        assert (rx_data_en===1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_data_en must be 0 when !(rx_in_P0 | rxX_reset | ((rx_handshake_req_active | rx_handshake_reset) & rxX_pstate ===00)) violation!");
    end
  end

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (rx_handshake_req_active===1'b1 ||  rx_handshake_reset===1'b1)) begin
      rx_adapt_afe_dfe_en_assert: 
        assert (rx_adapt_afe_en == rx_adapt_dfe_en);
        //else $display("PHY_INF_ASSERTION_ERROR: rxX_adapt_afe_en === rxX_adapt_dfe_en when (rx_handshake_req_active===1 | rx_handshake_reset===1) violation!");
    end
  end

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (rx_handshake_req_active===1'b1 && rx_adapt_afe_en===1'b1 && curr_rx_adapt_afe_en===1'b1)) begin
      rx_eq_bus_assert: 
        assert (rx_eq_bus == curr_rx_eq_bus);
        //else $display("PHY_INF_ASSERTION_ERROR: rxX_eq_<*> === curr_rxX_eq_<*> when (rx_handshake_req_active===1 & rxX_adapt_afe_en & curr_rxX_adapt_afe_en) violation!");
    end
  end

  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (!rx_in_P0 || !ref_clk_en || rx_handshake_req_active || rx_handshake_reset || phy_reset || rx_reset)) begin
      rx_adapt_req_assert: 
        assert (rx_adapt_req===1'b0);
        //else $display("PHY_INF_ASSERTION_ERROR: rx_adapt_req must be 0 if (!rx_in_P0 | ref_clk_en == 0 | rx_handshake_req_active | rx_handshake_reset | phy_reset | rx_reset) violation!");
    end
  end

  // not rx_reset and tx_reset in power gating
  always @(*) begin
    #1ps;
    if (lane_assertion_enabled && (tx_pg_reset_and_exit | rx_pg_reset_and_exit)) begin
      no_tx_rx_reset_in_pg_assert: 
        assert (!rx_reset && !tx_reset);
    end
  end


//----------------------------------------------------------------------
// SUP assertions
//----------------------------------------------------------------------
  logic clk_2ns;
  logic tx_mplla_on, tx_mpllb_on;

  initial begin
    clk_2ns = 1'b0;
  end

  //----------------------------------------------------------------------
  // Logic Implementation
  //----------------------------------------------------------------------
  always clk_2ns = #1ns ~clk_2ns;
  
  assign tx_mplla_on = curr_tx_mpll_en & !curr_tx_mpllb_sel & !tx_handshake_req_active & !tx_handshake_reset & !phy_reset & !tx_reset;
  assign tx_mpllb_on = curr_tx_mpll_en & curr_tx_mpllb_sel & !tx_handshake_req_active & !tx_handshake_reset & !phy_reset & !tx_reset;
  
  //----------------------------------------------------------------------
  // Assertion Implementation
  //----------------------------------------------------------------------
`ifndef ANI_SHORT_RESET
  phy_reset_pwr_up_assert:
    assert property (@(posedge clk_2ns) disable iff ((vph !== 1'b1) || test_mode || phy_reset_pwr_up_assert_dis)
      $rose(vph) |-> (phy_reset!==1'b1)[*0:500000] ##1 phy_reset[*5000:500000] ##1 !phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: phy_reset minimum assertion time after (rising edge of vph) = 10us (ANI_SHORT_RESET not defined) violation!", lane_assert);
`endif

  phy_reset_pulse_assert:
    assert property (@(posedge clk_2ns) disable iff (test_mode)
      $rose(phy_reset) |-> phy_reset[*5:500000] ##1 !phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: phy_reset any subsequenct assertion time > 10ns violation!", lane_assert);

  ref_use_pad_assert:
    assert property (@(ref_use_pad) disable iff (!assertions_enabled)
      phy_reset && !ref_clk_en);
    //else $display("PHY_INF_ASSERTION_ERROR: ref_use_pad must be stable when !(phy_reset) | (ref_clk_en===1) violation!");
  
  ref_clk_div2_en_assert:
    assert property (@(ref_clk_div2_en) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset && !ref_clk_en);
    //else $display("PHY_INF_ASSERTION_ERROR: ref_clk_div2_en must be stable when !(phy_reset) | (ref_clk_en===1) violation!");

  ref_range_assert:
    assert property (@(ref_range) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset && !ref_clk_en);
    //else $display("PHY_INF_ASSERTION_ERROR: ref_range must be stable when !(phy_reset) | (ref_clk_en===1) violation!");

  ref_clk_mplla_div2_en_assert:
    assert property (@(ref_clk_mplla_div2_en) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: ref_clk_mplla_div2_en must be stable when !(phy_reset) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  ref_clk_mpllb_div2_en_assert:
    assert property (@(ref_clk_mpllb_div2_en) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: ref_clk_mpllb_div2_en must be stable when !(phy_reset) violation!");
`endif

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mplla_multiplier_assert:
    assert property (@(mplla_multiplier) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_multiplier must be stable when !(phy_reset) violation!");
`else
	//for c8gen3 (single MPLL), tx_mpll_en should be low when there is
	//a change in mplla_multiplier value
   mplla_multiplier_assert:
    assert property (@(mplla_multiplier) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      !tx_mpll_en);
  `endif

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_multiplier_assert:
    assert property (@(mpllb_multiplier) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_multiplier must be stable when !(phy_reset) violation!");
`endif

  mplla_bandwidth_assert:
    assert property (@(mplla_bandwidth) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_bandwidth must be stable when !(phy_reset) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_bandwidth_assert:
    assert property (@(mpllb_bandwidth) disable iff (!assertions_enabled || isolate_en!==1'b0 || isolate_en_d!==1'b0)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_bandwidth must be stable when !(phy_reset) violation!");
`endif

  mplla_init_cal_disable_assert:
    assert property (@(mplla_init_cal_disable) disable iff (!assertions_enabled)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_init_cal_disable must be stable when !(phy_reset) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_init_cal_disable_assert:
    assert property (@(mpllb_init_cal_disable) disable iff (!assertions_enabled)
      phy_reset);
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_init_cal_disable must be stable when !(phy_reset) violation!");
`endif
  mplla_div8_clk_en_assert: 
    assert property (@(mplla_div8_clk_en) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_div8_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_div8_clk_en_assert: 
    assert property (@(mpllb_div8_clk_en) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_div8_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_div10_clk_en_assert: 
    assert property (@(mplla_div10_clk_en) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_div10_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_div10_clk_en_assert: 
    assert property (@(mpllb_div10_clk_en) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_div10_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_ssc_en_assert: 
    assert property (@(mplla_ssc_en) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_ssc_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_ssc_en_assert: 
    assert property (@(mpllb_ssc_en) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_ssc_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_ssc_range_assert: 
    assert property (@(mplla_ssc_range) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_ssc_range must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_ssc_range_assert: 
    assert property (@(mpllb_ssc_range) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_ssc_range must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_fracn_ctrl_assert: 
    assert property (@(mplla_fracn_ctrl) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_fracn_ctrl must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_fracn_ctrl_assert: 
    assert property (@(mpllb_fracn_ctrl) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_fracn_ctrl must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_ssc_clk_sel_assert: 
    assert property (@(mplla_ssc_clk_sel) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_ssc_clk_sel must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_ssc_clk_sel_assert: 
    assert property (@(mpllb_ssc_clk_sel) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_ssc_clk_sel must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_div_multiplier_assert: 
    assert property (@(mplla_div_multiplier) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_div_multiplier must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_div_multiplier_assert: 
    assert property (@(mpllb_div_multiplier) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_div_multiplier must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_div_clk_en_assert: 
    assert property (@(mplla_div_clk_en) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_div_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");

`ifndef DWC_E12MP_X4NS_MPLLB_NOT_PRESENT
  mpllb_div_clk_en_assert: 
    assert property (@(mpllb_div_clk_en) disable iff (!assertions_enabled)
      !(tx_mpllb_on || (tx_mpll_en && tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mpllb_div_clk_en must be stable when (tx_mpll{a,b}_on===1 | (tx_mpll_en===1 & tx_mpllb_sel==={0,1} & tx_handshake_active===1)) violation!");
`endif

  mplla_div16p5_clk_en_assert: 
    assert property (@(mplla_div16p5_clk_en) disable iff (!assertions_enabled)
      !(tx_mplla_on || (tx_mpll_en && !tx_mpllb_sel && tx_handshake_active)));
    //else $display("PHY_INF_ASSERTION_ERROR: mplla_div16p5_clk_en must be stable when (tx_mplla_on===1 | (tx_mpll_en===1 & tx_mpllb_sel===0 & tx_handshake_active===1)) violation!");
     
     
  always @ (posedge rtune_req)
  begin
     if(lane_assertion_enabled)
     begin
        assert(phy_reset_exit==0); 
	//assert(rtune_ack===0);
     end	
  end   
  always @ (negedge rtune_req)
  begin
     if(lane_assertion_enabled)
        assert(rtune_ack===1);
  end    
  always @ (pg_mode_en)
  begin
     if(lane_assertion_enabled)   
        assert(phy_reset===1);
  end  
  always @ (*)
  begin
     if(lane_assertion_enabled && !pcs_pwr_stable_assert_dis) begin
       if(~pg_mode_en | tx_in_P0 | tx_in_P0s | rx_in_P0 | rx_in_P0s | (tx_pstate<2 && tx_handshake_active) | (rx_pstate<2 && rx_handshake_active)) begin 
         pcs_pwr_stable_assert:
           assert(pcs_pwr_stable==1);
       end
     end
  end 

always @(*) begin
  if (~phy_reset && !tx_mpllb_sel && assertions_enabled)
    mplla_div8_10_exclusive: assert (!(mplla_div8_clk_en && mplla_div10_clk_en));
end

always@(*) begin
  if(~phy_reset && tx_mpllb_sel && assertions_enabled)
    mpllb_div8_10_exclusive: assert (!(mpllb_div8_clk_en && mpllb_div10_clk_en));
end

`ifdef DWC_C8_PMA
assign test_flyover_en = 0;
`endif

`ifdef DWC_E12MP_X4NS_PMA_FLYOVER 
always @(*) begin
 if(~phy_reset)
test_exclusive_signals    : assert ((test_powerdown && ~test_flyover_en && ~test_burnin && ~test_stop_clk_en) ||(~test_powerdown && test_flyover_en && ~test_burnin && ~test_stop_clk_en) || (~test_powerdown && ~test_flyover_en && test_burnin && ~test_stop_clk_en) ||(~test_powerdown && ~test_flyover_en && ~test_burnin && test_stop_clk_en)||(~test_powerdown && ~test_flyover_en && ~test_burnin && ~test_stop_clk_en)) ; 
end
`endif

endmodule
